The present invention broadly relates to reliability testing of integrated circuits during manufacture, and deals more particularly with a method and apparatus for stress testing integrated circuits using hot carrier injection.
Integrated circuits are manufactured by forming a multitude of individual chips in and on the surface of a semiconductor wafer. Upon completion, the wafer surface is typically covered with identical areas of patterning, with each area defining a single chip or integrated circuit, sometimes referred to as a die. The dies are separated from each other by regions that normally do not contain circuitry, which are commonly known as scribe lines. The areas defining the scribe line areas are eventually sawn through to separate the wafer into individual die.
Wafer fabrication requires a high degree of precision. One mistake can render an individual die or perhaps an entire wafer completely useless. Therefore, as the wafer proceeds through fabrication processing steps, it is subjected to a variety of tests and evaluations. Toward the end of the fabrication process, the IC devices are more fully characterized and tested before the wafer is converted into individual die, in order to determine their reliability and failure probability.
Early test equipment tested individual ICs on the wafer using needle-like probes which were positioned into contact with bonding pads on the IC""s in order to apply desired test voltages and currents. More recently, however, so-called on-wafer tests have been performed which function to carry out individual testing and characterization of individual IC""s, thereby eliminating the time consuming process of probing each die. In some cases, such test circuits are formed on each individual die, however the disadvantage of this approach lies in the xe2x80x9creal estatexe2x80x9d that must be devoted to the test circuitry. In other cases, test circuits are formed within the areas defining the scribe lines. This latter approach has the advantage of making more area of the wafer available for forming ICs, and thus generally allows more IC""s to be manufactured from each wafer.
As indicated above, part of the testing that is conducted on individual IC""s before the wafer is sawed into individual die relates to reliability. The ICs are subjected to various types of tests to determine and predict the reliability of the structure used for interconnections and transistors. These structures are placed under various dynamically varied environmental and other stress conditions. Typical tests include electromigration, stress migration, hot carrier injection and gate oxide integrity. Hot carrier degradation is of particular interest because, as devices are scaled to smaller geometries, the electric field between drain and source and across the oxide becomes larger, increasing the probability that impact ionization will occur and charged xe2x80x9chot carriersxe2x80x9d will create interface damage or be injected into the oxide. When interface damage or charge trapping occurs in the oxide, device performance may degrade to the point of circuit failure. In some cases, hot carrier damage causes the transistor transconductance to slowly degrade and eventually may cause the transistor""s threshold to change near the drain edge of the channel such that it cannot form a channel in the drain region. This mechanism can be more damaging to digital circuits because it will cause parts of the digital circuits to have longer delay than originally intended.
Self stressing test structures for determining susceptibility of an IC to hot carrier degradation are known in the art. These test structures typically employ an AC controlled oscillator which outputs a time varying voltage that is applied to test the IC. This AC controlled oscillator is sometimes referred to as an AC hot carrier injection stress test circuit and employs a standard ring oscillator which serves as a stable signal source, having a fixed frequency. It has been found that the application of a single pulse of fixed frequency to the device under test does not always produce an accurate prediction of the reliability or useful life of the device under test. This is because under actual operating circumstances, the device may be subject to multiple pulses of various durations and/or multiple frequencies which cause the device to respond much differently to possible hot carrier degradation. Accordingly, there is a need in the art for a method and apparatus for testing integrated circuits for their susceptibility to hot carrier injection degradation which overcomes the problems mentioned above and provides more accurate test results. The present invention is directed towards satisfying this need.
According to one aspect of the invention, an on-wafer, hot carrier test system for stressing integrated circuits is provided that includes an adjustable oscillator circuit and a modulator circuit. The oscillator circuit produces an alternating current test signal having a variable frequency, and the modulator circuit is adjustable in order to adjust the duty cycle of the test signal. The input of the oscillator circuit is coupled with an adjustable voltage source, such that the frequency of the test signal is related to the magnitude of the voltage applied to the oscillator circuit input. The modulator circuit includes an input connected with an adjustable voltage source, such that the length of the duty cycle is related to the magnitude of the coupled voltage applied to the modulator circuit input.
According to another aspect of the invention, a method is provided for stress testing integrated circuits formed on a semiconductor wafer using an on wafer, hot carrier injection source comprising the steps of: producing an AC test signal using an oscillator formed on the wafer, adjusting the frequency of the test signal, adjusting the duty cycle of the test signal and applying the test signal to integrated circuits formed on the wafer.
Accordingly, it is a primary object of the present invention to provide a novel method and apparatus for reliability testing of integrated circuits formed on a semiconductor wafer.
Another object of the invention is to provide a method and apparatus above in which the test structure is formed directly on the wafer as part of the semiconductor manufacturing process.
A further object of the invention is to provide a method and apparatus of the type described above which provides more robust testing of integrated circuits under wider dynamic test conditions in order to provide improved predictability of failure modes and service life.
A still further object of the invention is to provide a method and apparatus as described above which allows variation of both the frequency and duty cycle of test signals applied to the integrated circuits under test.
These, and further objects and advantages of the invention will be made clear or will become apparent during the course of the following description of a preferred embodiment of the invention.